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A RECONFIGURABLE MODULAR ARCHITECTURE TO EXPLOIT WORD-LEVEL PARALLELISM.
- Source :
- Journal of Circuits, Systems & Computers; Nov2009, Vol. 18 Issue 7, p1227-1241, 15p, 2 Diagrams, 5 Charts
- Publication Year :
- 2009
-
Abstract
- Contemporary memory system design aims to achieve high performance and low energy consumption at a reasonable cost. To balance these requirements, we propose a modular reconfigurable architecture to design memories over FPGAs. The proposed memory system can be reconfigured taking into account: the number of words, the word size of the data, the number of physical memory banks and the number of ports of the banks. Different operating modes have been defined, each one implying a certain configuration for the memory system. Simulations of these modes show the performance of our reconfigurable memory in terms of timing and power consumption. [ABSTRACT FROM AUTHOR]
- Subjects :
- MEMORY
DATA
ELECTRIC power
ELECTRONICS
POWER electronics
Subjects
Details
- Language :
- English
- ISSN :
- 02181266
- Volume :
- 18
- Issue :
- 7
- Database :
- Complementary Index
- Journal :
- Journal of Circuits, Systems & Computers
- Publication Type :
- Academic Journal
- Accession number :
- 44694912
- Full Text :
- https://doi.org/10.1142/S0218126609005630