Effects of Plasma-Induced Si Recess Structure on n-MOSFET Performance Degradation.

Performance degradation of n-MOSFETs with plasma-induced recess structure was investigated. The depth of Si recess (d_R) was estimated from the experiments by using Ar gas plasmas. We propose an analytical model by assuming that the damage layer was formed during an offset spacer etch. A linear relationship between threshold voltage shift (ΔV_th) and d_R was found. Device simulations were also performed for n-MOSFETs with various (d_R). Both ∣ΔV_th∣ and OFF-state leakage current increased with an increase in d_R. The increase in ∣ΔV_th∣ becomes larger for smaller gate length. The results from device simulations are consistent with the analytical model. These findings imply that the Si recess structure induced by plasma damage enhances V_th-variability in future devices. [ABSTRACT FROM AUTHOR]