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On-Chip Optical Interconnect.

Authors :
OHASHI, KEISHI
NISHI, KENICHI
SHIMIZU, TAKANORI
NAKADA, MASAFUMI
FUJIKATA, JUNICHI
USHIDA, JUN
TORII, SUNAO
NOSE, KOICHI
MIZUNO, MASAYUKI
YUKAWA, HIROAKI
KINOSHITA, MASAO
SUZUKI, NOBUO
GOMYO, AKIKO
ISHI, TSUTOMU
OKAMOTO, DAISUKE
FURUE, KATSUYA
UENO, TOSHIHIDE
TSUCHIZAWA, TAI
WATANABE, TOSHIFUMI
YAMADA, KOJI
Source :
Proceedings of the IEEE; Jul2009, Vol. 97 Issue 7, p1186-1198, 13p, 3 Black and White Photographs, 10 Diagrams, 3 Graphs
Publication Year :
2009

Abstract

We describe a cost-effective and low-power-consumption approach for on-chip optical interconnection. This approach includes an investigation into architectures, devices, and materials. We have proposed and fabricated a bonded structure of an Si-based optical layer on a large-scale integration (LSI) chip. The fabricated optical layer contains Si nanophotodiodes for optical detectors, which are coupled with SiON waveguides using surface-plasmon antennas. Optical signals were introduced to the optical layer and distributed to the Si nanophotodiodes. The output signals from the photodiodes were sent electrically to the transimpedance-amplifier circuitries in the LSI. The signals from the photodiodes triggered of the circuitries at 5 GHz. Since electrooptical modulators consume the most power in on-chip optical interconnect systems and require a large footprint, they are critical to establish on-chip optical interconnection. Two approaches are investigated: 1) an architecture using a fewer number of modulators and 2) high electrooptical coefficient materials. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00189219
Volume :
97
Issue :
7
Database :
Complementary Index
Journal :
Proceedings of the IEEE
Publication Type :
Academic Journal
Accession number :
42837583
Full Text :
https://doi.org/10.1109/JPROC.2009.2020331