Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems.

Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. These systems provide new opportunities for high-performance computing. However, the coexistence of the processors and the FPGAs in them also poses new challenges to application developers. In this paper, we build a design model for hybrid designs, that is, designs that utilize both the processors and the FPGAs for computations. The model characterizes a reconfigurable computing system using various parameters, including the floating-point computing power of the processors and the FPGAs, the number of nodes, the size of multiple levels of memory, the memory bandwidth, and the network bandwidth. Based on the model, we propose a design methodology for hardware/software codesign. The methodology partitions workload between the processors and the FPGAs, maintains load balance in the system, and realizes scalability over multiple nodes. Designs are proposed for several computationally intensive applications: matrix multiplication, matrix factorization, and the Floyd-Warshall algorithm for the all-pairs shortest-paths problem. To illustrate our ideas, the proposed hybrid designs are implemented on a Cray XD1. Each node of XD1 contains AMD 2.2-GHz Opteron processors and a Xilinx Virtex-II Pro FPGA. Experimental results show that our designs utilize both the processors and the FPGAs efficiently and overlap most of the data transfer overheads and network communication costs with the computations. Our designs achieve up to 90 percent of the total performance of the nodes and 90 percent of the performance predicted by the design model. In addition, our designs scale over a large number of nodes. [ABSTRACT FROM AUTHOR]