A Low-Power 512-Bit EEPROM Design for UHF RFID Tag Chips.

Authors :: Hutchison, David
Kanade, Takeo
Kittler, Josef
Kleinberg, Jon M.
Mattern, Friedemann
Mitchell, John C.
Naor, Moni
Nierstrasz, Oscar
Rangan, C. Pandu
Steffen, Bernhard
Sudan, Madhu
Terzopoulos, Demetri
Tygar, Doug
Vardi, Moshe Y.
Weikum, Gerhard
Shi, Yong
van Albada, Geert Dick
Dongarra, Jack
Sloot, Peter M. A.
Jae-Hyung Lee
Source :: Computational Science: ICCS 2007 (9783540725893); 2007, p721-724, 4p
Publication Year :: 2007
Abstract: In this paper, a design for a low-power 512-bit synchronous EEPROM with flash cells for passive UHF RFID tag chip is presented. Applied are low-power schemes such as dual power supply voltage(VDD=1.5V and VDDP=2.5V), clocked inverter sensing, voltage-up converter, IO interface, and Dickson charge pump using schottky diode. An EEPROM is fabricated with the 0.25μm- EEPROM process. Simulation results show that power dissipations are 8.34μW in the read cycle and 57.7μW in the write cycle, respectively. The layout size is 449.3μm × 480.67μm. [ABSTRACT FROM AUTHOR]