On the positive channel threshold voltage of metal gate electrodes on high-permittivity gate dielectrics.

Factors responsible for the undesirably high values of positive-channel (p-channel) threshold voltage (V_t) in high-κ metal oxide semiconductor transistors are investigated. In silicon/silicon dioxide/hafnium dioxide/metal gate transistors an anomalous nonlinear relationship between the equivalent oxide thickness (EOT) and V_t occurs when the silicon dioxide (SiO₂) interface layer is sufficiently thin (<2.3 nm). The deviation from the expected EOT versus V_t behavior is shown to be related to processing temperature, metal work-function, substrate doping type, and thickness of the high-κ material. This result, coupled with charge trapping measurements on samples with different SiO₂ interface layer thickness, suggests that the loss of negative fixed charge via the tunneling of trapped electrons to the substrate is a possible explanation for the elevated p-channel V_t. [ABSTRACT FROM AUTHOR]