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Compiler-Guided Leakage Optimization for Banked Scratch-Pad Memories.
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Oct2005, Vol. 13 Issue 10, p1136-1146, 11p, 4 Black and White Photographs, 14 Graphs
- Publication Year :
- 2005
-
Abstract
- Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 10638210
- Volume :
- 13
- Issue :
- 10
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Publication Type :
- Academic Journal
- Accession number :
- 19319693
- Full Text :
- https://doi.org/10.1109/TVLSI.2005.859478