Reliable 2-bit/cell NVM technology using twin SONOS memory transistor.

Authors :: Choi, B. Y.
Park, B.-G.
Lee, J. D.
Shin, H.
Lee, Y. K.
Bai, K. H.
Kim, D.-D.
Kim, D.-W.
Lee, C.-H.
Park, D.
Source :: Electronics Letters (Institution of Engineering & Technology); 9/15/2005, Vol. 41 Issue 19, p1086-1087, 2p
Publication Year :: 2005
Abstract: The twin SONOS memory (TSM) transistors for 2-bit/cell non-volatile-memory (NVM) application are presented and their reliability is evaluated so that they can be applied to next generation NVM technology. This new memory, which is implemented by the damascene gate and outer sidewall spacer processes, shows a high reliability down to 80 nm gate length. [ABSTRACT FROM AUTHOR]