Reducing Avalanche Build-Up Time by Integrating a Single-Photon Avalanche Diode with a BiCMOS Gating Circuit.

It is shown that the integration of a single-photon avalanche diode (SPAD) together with a BiCMOS gating circuit on one chip reduces the parasitic capacitance a lot and therefore reduces the avalanche build-up time. The capacitance of two bondpads, which are necessary for the connection of an SPAD chip and a gating chip, are eliminated by the integration. The gating voltage transients of the SPAD are measured using an integrated mini-pad and a picoprobe. Furthermore, the gating voltage transients of a CMOS gating circuit and of the BiCMOS gating circuit are compared for the same integrated SPAD. The extension of the 0.35 μ m CMOS process by an NPN transistor process module enabled the BiCMOS gating circuit. The avalanche build-up time of the SPAD is reduced to 1.6 ns due to the integration compared to about 3 ns for a wire-bonded off-chip SPAD using the same n + and p-well as well as the same 0.35 μ m technology. [ABSTRACT FROM AUTHOR]