Van der Waals polarity-engineered 3D integration of 2D complementary logic.

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1–3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6–8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe₂ (refs. 9–17) and MoS₂ (refs. 11,18–28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS₂, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS₂ can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm² V⁻¹ s⁻¹, on/off ratios reaching 10⁶ and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.We develop a method for high-density vertical stacking of active-device multi-layers, implementing memory and logic functions, using unique VIP-FETs where a van der Waals intercalation layer modulates the p- or n-type nature of the FETs. [ABSTRACT FROM AUTHOR]