Floorplanning for optimizing area using sequence pair and hybrid optimization.

Physical design is major key processes in integrating the circuit into the chip area in VLSI circuit design. A netlist is accepted as input by a floorplanning stage, provided by the physical design phase of splitting the circuits. The floor planner creates the best positions for the circuit module. The dimensions, size, and connectivity details of the modules are contained in the netlist. It is crucial to create an optimum floorplan by creating metaheuristic optimization algorithms to increase the circuit performance by reducing chip size, wire length, and peak temperature. This scheme always has a complexity to allocate the weights and might consequence in adverse bias with a specific intention. Here, the non-slicing floor plan is studied through the sequence pair (SP) method. SP is a method for packing the blocks using a pair of modules termed sequences. Consequently, optimal parameter (area and wire length) tuning is performed by a new hybrid Integrated Bald Eagle and SMO (IBE-SMO) scheme that combined the approaches such as BES and SMO for optimal FP by means of tuning the wire length and area, taking into consideration as multi-objective. This validates the optimization of wire length and area utilizing IBE-SMO to reduce the length, width and height of the floor plan area. The standard MCNC benchmark circuits were used to test the suggested technique, and the findings show that it decreases the area by 0.7 × 10⁴, and wire length by 0.84 × 10⁵, compared to the existing methods. [ABSTRACT FROM AUTHOR]