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Vector Accelerator Unit for Caravel.
- Source :
- IEEE Embedded Systems Letters; Mar2024, Vol. 16 Issue 1, p73-76, 4p
- Publication Year :
- 2024
-
Abstract
- Caravel is an open-source project developed by Efabless for creating custom system-on-chips (SoCs). It includes the design of a configurable chip, development tools, and documentation. The Caravel SoC includes a RISC-V with the Instruction Set Architecture RV32I. One of the key features of Caravel is its open-source nature. In this letter, the vector accelerator unit for the Caravel SoC template is presented to increase the RISC-V capabilities, allowing parallel data processing through 14 vector operations. The accelerator is based on 4 Arithmetic Logic Units connected directly to the RISC-V through the logic analyzer port and the general-purpose input/output (GPIO) port. The total area of this accelerator is less than 20% of the User Project Wrapper area allowing the user to implement their custom designs in 8.4256 mm2. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 19430663
- Volume :
- 16
- Issue :
- 1
- Database :
- Complementary Index
- Journal :
- IEEE Embedded Systems Letters
- Publication Type :
- Academic Journal
- Accession number :
- 175943058
- Full Text :
- https://doi.org/10.1109/LES.2023.3267341