Van der Waals Heterostructure Engineering for Ultralow-Resistance Contact in 2D Semiconductor P-Type Transistors.

Achieving a low resistance contact is essential for developing two-dimensional (2D) material-based field-effect transistors (FETs). While n-type contacts to 2D semiconductors have been studied, understanding and designs for p-type contacts to 2D semiconductors remain very limited. In this study, we propose and computationally explore three strategies to improve the contact resistance in p-type 2D FETs, which remains a critical bottleneck of 2D logic technology, through the engineering of van der Waals (vdW) material heterostructures: (i) intercalating a graphene layer between a high-work-function metal and 2D semiconductor, which can result in low contact resistance of ~ 60 Ω μm for the graphene-intercalated contact between a high-work-function metal and WSe₂ semiconductor; (ii) engineering the atomic stacking order between a vdW metal and 2D semiconductor, which can result in contact resistance of ~ 50 Ω μm; (iii) sandwiching the 2D layered semiconductor between vdW metals from both sides, which can further reduce the contact resistance to ~ 47 Ω μm and ~ 36 Ω μm for cases (i) and (ii), respectively. Experimental fabrication and characterization illustrate the feasibility of structural engineering of contacts. The above structural designs can lead to significantly reduced metal-induced gap states (MIGS) and low barrier height for holes, resulting in low contact resistance. They are also naturally compatible with the gate-all-around (GAA) transistor structure. In addition to contact materials selection, vdW structural design offers an alternative approach for achieving low contact resistance to p-type 2D FETs. [ABSTRACT FROM AUTHOR]