FPGA Implementation of IEC 61131-3-Based Hardware-Aided Timers for Programmable Logic Controllers.

Designs of timer function blocks (FBs) are presented in the article. The developed modules are IEC 61131-3. An analysis of IEC 61131-3 in terms of timer functionality and implementation options is presented. Three types are presented, timer-on, timer-off, and timer-pulse, with each type designed to be fully hardware or software-like. Both designs, hardware or software-like, can operate as multi-channel timers. Particularly noteworthy is the software-like design, for which a solution without edge detectors was achieved. Such a feature was obtained by reversing the method of time determination by counting the difference between the start and end times and by using specific features of the D flip-flops, that is, clock-enable inputs. The presented timers were written in Verilog language and implemented in an FPGA chip. Thanks to the universal design of the interface, the proposed FBs can be used for the hardware support of existing programmable logic controllers (PLCs) or as an integral part of newly built PLC CPUs. The idea of a CPU architecture with hardware support is proposed. The paper presents the results of the implementation in an FPGA of the Kintex UltraScale+ family from AMD-Xilinx. [ABSTRACT FROM AUTHOR]