Property Analysis of Gateway Refinement of Object-Oriented Petri Net with Inhibitor-Arcs-Based Representation for Embedded Systems.

MLA

Xia, Chuanliang, et al. “Property Analysis of Gateway Refinement of Object-Oriented Petri Net with Inhibitor-Arcs-Based Representation for Embedded Systems.” Electronics (2079-9292), vol. 12, no. 18, Sept. 2023, p. 3977. EBSCOhost, https://doi.org/10.3390/electronics12183977.

APA

Xia, C., Qin, M., Sun, Y., & Guo, M. (2023). Property Analysis of Gateway Refinement of Object-Oriented Petri Net with Inhibitor-Arcs-Based Representation for Embedded Systems. Electronics (2079-9292), 12(18), 3977. https://doi.org/10.3390/electronics12183977

Chicago

Xia, Chuanliang, Mengying Qin, Yan Sun, and Maibo Guo. 2023. “Property Analysis of Gateway Refinement of Object-Oriented Petri Net with Inhibitor-Arcs-Based Representation for Embedded Systems.” Electronics (2079-9292) 12 (18): 3977. doi:10.3390/electronics12183977.