Optimized buffer insertion using PSO technique for efficient interconnect designs.

This paper describes the buffer optimisation strategy adopted for designing efficient interconnects at 14nm and 7nm technology regime. Investigations are carried out at different wire lengths; ranging from 500 µm to 2000 µm for Cu as well as CNT interconnects. The particle swarm optimization (PSO) methodology is adopted for computing optimus repeater count and size. The results obtained are then validated by comparing it with analytically computed results. The result analysis points out that delay-minimal buffer design strategy may sometimes results in excessive insertion of repeaters, henceforth causing significant power consumption. Thus figure of merit is calculated to investigate the tradeoff between delay and power for Cu and CNT interconnects. From the results it was observed that for carbon nanotube interconnects the quantity of buffers needed is much less as compared to Cu interconnects. For both types of interconnects it is investigated that mere advancement in technology node results in significant increase of buffers to be inserted as repeater. [ABSTRACT FROM AUTHOR]