Electrical passivation of stacking-fault crystalline defects in MOS capacitors on cubic silicon carbide (3C-SiC) by post-deposition annealing.

The interfacial electrical properties of deposited oxide (SiO₂) onto cubic silicon carbide (3C-SiC) were investigated after different post-oxide deposition annealing (PDA) by means of metal–oxide–semiconductor (MOS) capacitors and nanoscale capacitance mapping. The deposited oxides subjected to PDA at 450 °C in either nitrogen or forming gas showed a reduction of the interface and oxide traps, as well as an improved oxide field strength compared to the thermally grown insulating layer. Spatially resolved nanoscale capacitance mapping performed onto the oxide surface revealed that the density of the electrically active stacking faults (SFs) in 3C-SiC is diminished by appropriate PDA. The results pave the way to obtain an ideal SiO₂/3C-SiC system suitable for power device applications. [ABSTRACT FROM AUTHOR]