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Congestion aware low power on chip protocols with network on chip with cloud security.

Authors :
Ponnan, Suresh
Kumar, Tikkireddi Aditya
VS, Hemakumar
Natarajan, Sakthieswaran
Shah, Mohd Asif
Source :
Journal of Cloud Computing (2192-113X); 9/9/2022, Vol. 11 Issue 1, p1-10, 10p
Publication Year :
2022

Abstract

This article is to analyze the bottleneck problems of NoC in many more applications like multi-processor communication, computer architectures, and network interface processors. This paper aims to research the advantages and disadvantages of low congestion protocols on highway environments like multiple master multiple slave interconnections. A long-term evolution and effective on-chip connectivity solution for secured, congestion aware and low power architecture is emerged for Network-on-Chip (NoC) for MCSoC. Applications running simultaneously on a different chip are often exchanged dynamically on the chip network. Of-course, in general on chip communication, resources mean that applications may interact with shared resources to influence each other's time characteristics. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
2192113X
Volume :
11
Issue :
1
Database :
Complementary Index
Journal :
Journal of Cloud Computing (2192-113X)
Publication Type :
Academic Journal
Accession number :
159000347
Full Text :
https://doi.org/10.1186/s13677-022-00307-4