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Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets.
- Source :
- Micromachines; Jul2022, Vol. 13 Issue 7, pN.PAG-N.PAG, 6p
- Publication Year :
- 2022
-
Abstract
- A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring oscillator (RO) gained up to 27.8% improvement of delay with the same power consumption, for a 3-layer stacked GAA NS-FETs. Furthermore, the proposed S/D trimming technology could enable more than 4-layer vertical stacking of nanosheets for GAA technology extension beyond 3 nm CMOS technology. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 2072666X
- Volume :
- 13
- Issue :
- 7
- Database :
- Complementary Index
- Journal :
- Micromachines
- Publication Type :
- Academic Journal
- Accession number :
- 158298746
- Full Text :
- https://doi.org/10.3390/mi13071080