A 9.8–12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit.

MLA

Song, Shuxiang, et al. “A 9.8–12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit.” Journal of Circuits, Systems & Computers, vol. 31, no. 11, July 2022, pp. 1–14. EBSCOhost, https://doi.org/10.1142/S0218126622501900.

APA

Song, S., Liu, Z., Cen, M., & Cai, C. (2022). A 9.8–12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit. Journal of Circuits, Systems & Computers, 31(11), 1–14. https://doi.org/10.1142/S0218126622501900

Chicago

Song, Shuxiang, Zefa Liu, Mingcan Cen, and Chaobo Cai. 2022. “A 9.8–12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit.” Journal of Circuits, Systems & Computers 31 (11): 1–14. doi:10.1142/S0218126622501900.