A 9T high-stable and Low-Energy Half-Select-Free SRAM Cell Design using TMDFETs.

The revolution in technology is so fast that even silicon devices are not able to meet the current demand of high speed, low power, and minimal area. The CMOS SRAM cells are the ones, affected the most by the revolutionary scaling of the devices. Due to various limitations of CMOS in deep sub-micron, new devices have emerged. One such device is the transition metal dichalcogenide field-effect transistor (TMDFET) to have prominent properties. This paper presents a novel read decoupled feedback-cutting 9T (RDFC9T) SRAM cell with high static noise margins (SNMs). The 16 nm CMOS and TMDFET devices are being used to design and compare the proposed design, showing the superiority of the TMDFET-based design. Furthermore, to evaluate the comparative performance of the proposed RDFC9T SRAM cell, it has been compared with the published SRAM cells introduced as 6T, 10T-P1, HFSE9T, and SB11T redesigned by 10 nm TMDFET device at V_DD=0.7 V. The suggested cell exhibits 3.20X and 1.71X/1.15X/5.26X higher read SNM and write SNM as compared to the 6T and 6T/HFSE9T/10T-P1 SRAM cells, respectively. The cell exhibits 1.11X/2.10X and 1.06X/1.30X smaller read delay (T_RA) and write delay (T_WA) than that of the HFSE9T/SB11T SRAM design, correspondingly. In terms of power performance, the RDFC9T cell shows 0.86X/0.68X and 0.56X/0.37X/0.35X less read power and write power than the SB11T/6T and SB11T/10T-P1/6T cell, respectively. Moreover, the proposed design shows robustness against harsh process variations and mitigates the half-select issues to support bit-interleaving architecture. Here, we have also shown the layout of the projected RDFC9T cell and a comparison with the published designs. [ABSTRACT FROM AUTHOR]