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HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation.

Authors :
Hanchen Ye
Xiaofan Zhang
Zhize Huang
Gengsheng Chen
Deming Chen
Source :
DAC: Annual ACM/IEEE Design Automation Conference; 2020, Issue 57, p758-763, 6p
Publication Year :
2020

Abstract

To speedup Deep Neural Networks (DNN) accelerator design and enable effective implementation, we propose HybridDNN, a framework for building high-performance hybrid DNN accelerators and delivering FPGA-based hardware implementations. Novel techniques include a highly flexible and scalable architecture with a hybrid Spatial/Winograd convolution (CONV) Processing Engine (PE), a comprehensive design space exploration tool, and a complete design flow to fully support accelerator design and implementation. Experimental results show that the accelerators generated by HybridDNN can deliver 3375.7 and 83.3 GOPS on a high-end FPGA (VU9P) and an embedded FPGA (PYNQ-Z1), respectively, which achieve a 1.8x higher performance improvement compared to the state-of-art accelerator designs. This demonstrates that HybridDNN is flexible and scalable and can target both cloud and embedded hardware platforms with vastly different resource constraints. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
0738100X
Issue :
57
Database :
Complementary Index
Journal :
DAC: Annual ACM/IEEE Design Automation Conference
Publication Type :
Conference
Accession number :
155539763