Design of Low Leakage 9T SRAM Cell with Improved Performance for Ultra-Low Power Devices.

In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by 1. 6 5 × and 1. 8 4 × as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by 1. 5 8 × , 1. 4 0 × , 1. 4 7 × , 1. 0 5 × , 1. 5 7 × and 1. 3 1 × as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has 2. 2 × and 1. 6 3 × higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio ( I on ∕ I off ) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies 1. 2 0 × large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3 V supply voltage. [ABSTRACT FROM AUTHOR]