Highly-Doped Region Optimization for Reduced Hot-Carrier Effects in Dual-Gate Low Temperature Polysilicon TFTs.

MLA

Chen, Jian-Jie, et al. “Highly-Doped Region Optimization for Reduced Hot-Carrier Effects in Dual-Gate Low Temperature Polysilicon TFTs.” IEEE Electron Device Letters, vol. 42, no. 12, Dec. 2021, pp. 1794–97. EBSCOhost, https://doi.org/10.1109/LED.2021.3124910.

APA

Chen, J.-J., Chen, P.-H., Chang, T.-C., Tu, Y.-F., Zhou, K.-J., Kuo, C.-W., Hung, W.-C., Wu, P.-Y., & Huang, H.-C. (2021). Highly-Doped Region Optimization for Reduced Hot-Carrier Effects in Dual-Gate Low Temperature Polysilicon TFTs. IEEE Electron Device Letters, 42(12), 1794–1797. https://doi.org/10.1109/LED.2021.3124910

Chicago

Chen, Jian-Jie, Po-Hsun Chen, Ting-Chang Chang, Yu-Fa Tu, Kuan-Ju Zhou, Chuan-Wei Kuo, Wei-Chun Hung, Pei-Yu Wu, and Hui-Chun Huang. 2021. “Highly-Doped Region Optimization for Reduced Hot-Carrier Effects in Dual-Gate Low Temperature Polysilicon TFTs.” IEEE Electron Device Letters 42 (12): 1794–97. doi:10.1109/LED.2021.3124910.