Design and FPGA Implementation of Real-Time Edge Detectors Based on Interval Type-2 Fuzzy Systems.

The present work presents a hardware architecture design for real- time edge detection based on Interval Type-2 fuzzy systems. The proposed architecture is designed in order to be implemented on FPGAs, taking advantage of the parallelism, pipelining and fixed-point notation strategies. The proposed approach of hardware implementation is put forward because one of the main obstacles of Interval Type-2 fuzzy systems in applications is that they require a high processing rate and this kind of systems demands a high computational cost. The proposed approach is evaluated in three aspects, the first aspect is the processing rate, the proposed architecture must be able to realize at least 24 frames per second of edge detection, that corresponds to a real-time edge detection, the second aspect is their noise robustness, and the third aspect is the error with respect to the software implementation, and this is relevant because the proposed architecture handles the data at a binary level and there exist an inherent error in the hardware implementation. [ABSTRACT FROM AUTHOR]