A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.

MLA

Si, Xin, et al. “A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 66, no. 11, Nov. 2019, pp. 4172–85. EBSCOhost, https://doi.org/10.1109/TCSI.2019.2928043.

APA

Si, X., Khwa, W.-S., Chen, J.-J., Li, J.-F., Sun, X., Liu, R., Yu, S., Yamauchi, H., Li, Q., & Chang, M.-F. (2019). A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 66(11), 4172–4185. https://doi.org/10.1109/TCSI.2019.2928043

Chicago

Si, Xin, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, and Meng-Fan Chang. 2019. “A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 66 (11): 4172–85. doi:10.1109/TCSI.2019.2928043.