A SPICE Compatible Compact Model for Hot-Carrier Degradation in MOSFETs Under Different Experimental Conditions.

A compact hot-carrier degradation (HCD) time kinetics model is proposed for conventional, lightly doped drain, and drain extended MOSFETs and FinFETs. It can predict measured data obtained using different methods such as shift in threshold voltage ($\Delta {V}_{\text {T}}$), linear ($\Delta {I}_{\text {DLIN}}$) and saturation ($\Delta {I}_{\text {DSAT}}$) drain current, and charge pumping current ($\Delta {I}_{\text {CP}}$), for off- and on-state stress conditions. The influences of the gate $({V}_{\text {G}}$) and drain (${V}_{\text {D}}$) bias for large ${V}_{\text {D}}$ range and wide ${V}_{\text {G}}/{V}_{\text {D}}$ combinations, temperature (${T}$), and channel length $({L}_{\text {CH}}$) have been analyzed. The impact of ${L}_{\text {CH}}$ variation on ${V}_{\text {G}}$ dependence of HCD has been modeled. The model parameters are listed for different devices. [ABSTRACT FROM AUTHOR]