A 14-bit 250 kS/s two-step inverter-based incremental ΣΔ ADC for CMOS image sensor in 0.18μm technology.

This paper presents a 14-bit Incremental Sigma-Delta (ΣΔ) analog-to-digital converter suitable for column wise integration in a CMOS image sensor. A two step conversion is performed to improve the conversion speed. As the same ΣΔ modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier facilitates the integration within the column pitch and decreases power consumption. MonteCarlo simulations have been done in order to validate the design of the inverter. The proposed ADC is designed in 0.18μm CMOS technology. The simulation is performed with a 1.8 V voltage supply, a 20 MHz system clock frequency and an oversampling ratio (OSR) of 70, and achieves a power consumption is 460μW, a SNDR of 85.4 dB at a sampling rate of 250 kS/s. [ABSTRACT FROM AUTHOR]