LEAKAGE POWER REDUCTION USING MULTI MODAL DRIVEN HIERARCHICAL POWER MODE SWITCHES.

This article presents a scalable power-gating scheme approach to reduce leakage power using intermediate poweroff modes. An important limitation in power-gating scheme is its variations with wakeup time during activation mode changes, as is often the case. The authors have proposed a novel power-gating scheme that are accomplished by hierarchical mode activation to reduce worst case delay bound. The system combines the advantages of leakage power reduction and wake up time optimization. The influence of power-gating scheme on circuit performance is studied and concluded that finite power-off modes, scalable modes are important for good performance. Key selection of power-off modes over entire circuit is complex and it is computationally more expensive. To get more accurate modes with finite trade off in wake up time, this new approach gives near-perfect ways of isolating modes from other changes. The complete power-gating scheme system was evaluated on a multiplier logic core as a test sample and also compared against well known power-gating schemes. [ABSTRACT FROM AUTHOR]