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A Digital Implementation of Extreme Learning Machines for Resource-Constrained Devices.
- Source :
- IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Aug2018, Vol. 65 Issue 8, p1104-1108, 5p
- Publication Year :
- 2018
-
Abstract
- The availability of compact digital circuitry for the support of neural networks is a key requirement for resource-constrained embedded systems. This brief tackles the implementation of single hidden-layer feedforward neural networks, based on hard-limit activation functions, on reconfigurable devices. The resulting design strategy relies on a novel learning procedure that inherits the approach adopted in the Extreme Learning Machine paradigm. The eventual training process balances accuracy and network complexity effectively, thus supporting a digital architecture that prioritizes area utilization over computational performance. Experimental tests confirm that the design approach leads to efficient digital implementations of the predictor on low-performance devices. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15497747
- Volume :
- 65
- Issue :
- 8
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part II: Express Briefs
- Publication Type :
- Academic Journal
- Accession number :
- 131047002
- Full Text :
- https://doi.org/10.1109/TCSII.2018.2806085