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Energy-Efficient Design of Hybrid MTJ/CMOS and MTJ/Nanoelectronics Circuits.
- Source :
- IEEE Transactions on Magnetics; Jul2018, Vol. 54 Issue 7, p1-8, 8p
- Publication Year :
- 2018
-
Abstract
- As CMOS technology scales down to the nanoscale, high leakage power consumption becomes one of the major concerns in the design of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory (LIM) structures are being studied. Magnetic tunnel junction (MTJ) is an emerging spin-based device, which consumes very minimal leakage power in conjunction with CMOS transistors. In this paper, we propose a novel MTJ/CMOS design, which consumes low power and has lower delay than the existing LIM-based MTJ/CMOS designs. The proposed MTJ/CMOS designs have lower power and lower delay by charge sharing the output nodes during the pre-charge phase. The designs are simulated using 45 nm CMOS technology with perpendicular anistropy CoFeB/MgO MTJ model using a Cadence Spectre simulator. From the simulation results, we can see that the proposed MTJ/CMOS OR, AND, XOR, MUX, and full adder designs have 31.35%, 40.15%, 49.17%, 35.86%, and 42.62% lower power-delay-product, respectively, compared with the existing MTJ/CMOS designs. Furthermore, in this paper, we have also studied the usage of integrating nano-electronic devices, such as a carbon nanotube field-effect transistor and a Fin field-effect transistor, in the proposed circuits along with the MTJ devices. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189464
- Volume :
- 54
- Issue :
- 7
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Magnetics
- Publication Type :
- Academic Journal
- Accession number :
- 130317166
- Full Text :
- https://doi.org/10.1109/TMAG.2018.2833431