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Junctionless tri-gate InGaAs MOSFETs.

Authors :
Cezar B. Zota
Mattias Borg
Lars-Erik Wernersson
Erik Lind
Source :
Japanese Journal of Applied Physics; Dec2017, Vol. 56 Issue 12, p1-1, 1p
Publication Year :
2017

Abstract

We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L<subscript>g</subscript> = 25 nm at a nanowire dimension of 7 × 16 nm<superscript>2</superscript>. These devices use a single 7-nm-thick In<subscript>0.80</subscript>Ga<subscript>0.20</subscript>As (N<subscript>D</subscript> = 1 × 10<superscript>19</superscript> cm<superscript>−3</superscript>) layer as both channel and contacts. The devices show SS<subscript>sat</subscript> = 76 mV/dec, peak g<subscript>m</subscript> = 1.6 mS/µm and I<subscript>ON</subscript> = 160 µA/µm (at I<subscript>OFF</subscript> = 100 nA/µm and V<subscript>DD</subscript> = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00214922
Volume :
56
Issue :
12
Database :
Complementary Index
Journal :
Japanese Journal of Applied Physics
Publication Type :
Academic Journal
Accession number :
126394763
Full Text :
https://doi.org/10.7567/JJAP.56.120306