Guest Editorial Special Section on the IEEE International Conference on Microelectronic Test Structures.

Semiconductor Devices have been, and continue to be, the core of the information society. Together with tiny and inexpensive sensors, huge amounts of physical data will be collected in cyber-systems and analyzed by artificial intelligence. In such cyber-physical system, large-scale, low-power, and reliable semiconductor devices should be integrated with sensors and actuators. In addition to the classical trend of semiconductors, the engineers of mid-2010s must explore many materials for “new functionality,” whose impact on standard LSI system is still unclear. Recent integration technology such as chip-on-chip (3-D stacked IC) increases complexity of the device fabrication and analysis. It is therefore clear that everyone must seek for reliable and productive fabrication to achieve satisfactory yields, and a key component in addressing these issues is the characterization of the technology. Test structures, as well as test methods, play a major role in technology characterization and covers elements such as feature size measurement, parameter extraction, fluctuation assessment in transistors, stability measurement, and analogue parameter characterization. For thirty years the IEEE has annually sponsored the IEEE International Conference on Microelectronic Test Structures to discuss cutting edge methods in characterization. [ABSTRACT FROM PUBLISHER]