Optimization of Duplication-Based Schedules on Network-on-Chip Based Multi-Processor System-on-Chips.

Many applications such as streaming applications are both computation and communication intensive. The Multi-Processor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) outperforms the multiprocessors with bus-based networking architecture in communication bandwidth and scalability, making it a better choice for implementing systems running these applications. It's important to schedule both the computation and communication onto processors and the networking architecture so as to satisfy the stringent timing requirements. To reduce or avoid inter-processor communication, task duplication has been employed in scheduling. Most of the available techniques for the duplication-based scheduling problem use heuristics to solve the problem, and seldom has any work studied further improving the schedule performance, despite the fact that the heuristic cannot provide quality guarantee. To fill in this gap, this paper introduces a duplication and mapping constrained task-communication co-scheduling problem that assumes the duplication strategy and task-to-processor mapping are known a priory, and proposes two Integer Linear Programming (ILP) formulations, i.e., CF-ILP and CA-ILP, to solve two editions of this problem, i.e., the contention-free problem and the contention-aware problem. The proposed ILP formulations optimize the ordering and timing of the communication and computation, thus improving the performance. Both synthesized and real applications are tested on a set of platforms to evaluate the performance of the proposed methods. The experimental results demonstrate the effectiveness of the proposed methods. [ABSTRACT FROM PUBLISHER]