Cite
Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems.
MLA
Qiu, Keni, et al. “Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems.” IEEE Transactions on Computers, vol. 65, no. 7, July 2016, pp. 2313–24. EBSCOhost, https://doi.org/10.1109/TC.2015.2479605.
APA
Qiu, K., Li, Q., Hu, J., Zhang, W., & Xue, C. J. (2016). Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems. IEEE Transactions on Computers, 65(7), 2313–2324. https://doi.org/10.1109/TC.2015.2479605
Chicago
Qiu, Keni, Qingan Li, Jingtong Hu, Weigong Zhang, and Chun Jason Xue. 2016. “Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems.” IEEE Transactions on Computers 65 (7): 2313–24. doi:10.1109/TC.2015.2479605.