Cite
Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation.
MLA
Gangopadhyay, Dipanwita, and Arash Reyhani-Masoleh. “Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation.” IEEE Transactions on Computers, vol. 65, no. 7, July 2016, pp. 2143–57. EBSCOhost, https://doi.org/10.1109/TC.2015.2479617.
APA
Gangopadhyay, D., & Reyhani-Masoleh, A. (2016). Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation. IEEE Transactions on Computers, 65(7), 2143–2157. https://doi.org/10.1109/TC.2015.2479617
Chicago
Gangopadhyay, Dipanwita, and Arash Reyhani-Masoleh. 2016. “Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation.” IEEE Transactions on Computers 65 (7): 2143–57. doi:10.1109/TC.2015.2479617.