iitRACE: A memory efficient engine for fast incremental timing analysis and clock pessimism removal.

MLA

Peddawad, Chaitanya, et al. “IitRACE: A Memory Efficient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal.” 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Jan. 2015, pp. 903–09. EBSCOhost, https://doi.org/10.1109/ICCAD.2015.7372667.

APA

Peddawad, C., Goel, A., Dheeraj B, & Chandrachoodan, N. (2015). iitRACE: A memory efficient engine for fast incremental timing analysis and clock pessimism removal. 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 903–909. https://doi.org/10.1109/ICCAD.2015.7372667

Chicago

Peddawad, Chaitanya, Aman Goel, Dheeraj B, and Nitin Chandrachoodan. 2015. “IitRACE: A Memory Efficient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal.” 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), January, 903–9. doi:10.1109/ICCAD.2015.7372667.