On the architecture for the X part of a very large FX correlator using two-accumulator CMACs.

This paper presents an improved input-buffer architecture for the X part of a very large FX correlator that optimizes memory use to both increase performance and reduce the overall power consumption. The architecture uses an array of two-accumulator CMACs that are reused for different pairs of correlated signals. Using two accumulators in every CMAC allows the processing array to alternately correlate two sets of signal pairs selected in such a way so that they share some or all of the processed data samples. This leads to increased processing bandwidth and a significant reduction of the memory read rate due to not having to update some or all of the processing buffers in every second processing cycle. The overall memory access rate is at most 75 % of that of the single-accumulator CMAC array. This architecture is intended for correlators of very large multi-element radio telescopes such as the Square Kilometre Array (SKA), and is suitable for an ASIC implementation. [ABSTRACT FROM AUTHOR]