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VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standard.
- Source :
- 2015 25th International Workshop on Power & Timing Modeling, Optimization & Simulation (PATMOS); 2015, p71-76, 6p
- Publication Year :
- 2015
Details
- Language :
- English
- ISBNs :
- 9781467394192
- Database :
- Complementary Index
- Journal :
- 2015 25th International Workshop on Power & Timing Modeling, Optimization & Simulation (PATMOS)
- Publication Type :
- Conference
- Accession number :
- 112650280
- Full Text :
- https://doi.org/10.1109/PATMOS.2015.7347589