Enhancing the Reliability of Combinational Circuits by Adding Redundancy Using Fault Tree Analysis.

Reliability analysis of digital circuits is becoming a vital feature in the design process of nano-scale systems. Considering the relation between circuit and its reliability allows the designer to implement some compromises that can improve the resulting design. This paper presents a fault tree that computes the reliability of combinational logic circuits relating to single and multiple faults. The paper also presents gate redundancy architecture towards increasing the reliability of individual digital logic gates. It focuses on deriving the fundamental relationship between gate replication and reliability improvement and reports the experimental results. [ABSTRACT FROM AUTHOR]