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Verification of Transactional Memory in POWER8.
- Source :
- DAC: Annual ACM/IEEE Design Automation Conference; 2014, p329-334, 6p
- Publication Year :
- 2014
-
Abstract
- Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 0738100X
- Database :
- Complementary Index
- Journal :
- DAC: Annual ACM/IEEE Design Automation Conference
- Publication Type :
- Conference
- Accession number :
- 108916731
- Full Text :
- https://doi.org/10.1145/2593069.2593241