A Novel Approach Using Discrete Grain-Boundary Traps to Study the Variability of 3-D Vertical-Gate NAND Flash Memory Cells.

The 3-D NAND flash memory architectures will be a future trend, because they provide high memory capacity without aggressively scaling down. A vertical-gate (VG) structure composed of polysilicon (poly-Si) channels is a promising 3-D structure that could facilitate realizing an extremely tight-pitch NAND flash memory cell with high memory capacity. However, the variability of the VG memory cell induced by grain boundaries in the poly-Si channels is a major concern for aggressively scaled-down memory cells. In this paper, a discrete-trap approach is applied to emulate the real trap effects in a 3-D memory cell, and the 3-D structure geometry effects and the variation in the threshold voltage ( VT) induced by the discrete grain-boundary traps are studied. Various \Delta VT behaviors related to the structure geometry and trap position are examined. The effect of varying the body thickness on the \Delta VT is stronger than that of varying the channel width. This paper presents various cases for using the discrete-trap approach to study the variability of VT in 3-D VG memory cells. [ABSTRACT FROM AUTHOR]