Cite
3D IC process development for enabling chip-on-chip and chip on wafer multi-stacking at assembly.
MLA
Daily, R., et al. “3D IC Process Development for Enabling Chip-on-Chip and Chip on Wafer Multi-Stacking at Assembly.” 2015 International Conference on Electronic Packaging & IMAPS All Asia Conference (ICEP-IAAC), Jan. 2015, pp. 56–60. EBSCOhost, https://doi.org/10.1109/ICEP-IAAC.2015.7111000.
APA
Daily, R., Capuz, G., Wang, T., Bex, P., Struyf, H., Sleeckx, E., Demeurisse, C., Attard, A., Eberharter, W., & Klingler, H. (2015). 3D IC process development for enabling chip-on-chip and chip on wafer multi-stacking at assembly. 2015 International Conference on Electronic Packaging & IMAPS All Asia Conference (ICEP-IAAC), 56–60. https://doi.org/10.1109/ICEP-IAAC.2015.7111000
Chicago
Daily, R., G. Capuz, T. Wang, P. Bex, H. Struyf, E. Sleeckx, C. Demeurisse, A. Attard, W. Eberharter, and H. Klingler. 2015. “3D IC Process Development for Enabling Chip-on-Chip and Chip on Wafer Multi-Stacking at Assembly.” 2015 International Conference on Electronic Packaging & IMAPS All Asia Conference (ICEP-IAAC), January, 56–60. doi:10.1109/ICEP-IAAC.2015.7111000.