High performance 8 bit cascaded carry look ahead adder with precise power consumption.

Multiple bit adders like ripple carry adder make the propagation of carry bit very slow and this is the reason why it must be replaced with fast adders as carry-look-ahead adder (CLA). Power consumption in digital circuits depends on the number of metal-oxide-semiconductor field-effect transistor employed and various other parameters. If number of metal-oxide-semiconductor field-effect transistor is reduced the power consumption would definitely be reduced. Conventional CLAs would consume significant amount of power that still needs to be improved. The paper here deals with the implementation of 8 bit CLA with the aim of reducing the size and to precise the power consumption within nanowatt range, by improving the fundamental components of the circuit. All the parameters have been calculated by using Cadence Virtuoso tool at 45 nm technology. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]