Methodologies for power analysis attacks on hardware implementations of AES

Side Channel Attacks (SCA) exploit weaknesses in implementations of cryptographic functions resulting from unintended inputs and outputs such as execution timing, power consumption, electromagnetic radiation, thermal and acoustic emanations. Power Analysis Attacks (PAA) are a type of SCA in which an attacker measures the power consumption of a cryptographic device during normal execution. An attempt is then made to uncover a relationship between the instantaneous power consumption and secret key information. PAAs can be subdivided into Simple Power Analysis (SPA), Differential Power Analysis (DPA), and Correlation Power Analysis (CPA). Many attacks have been documented since PAAs were first described in 1998. But since they often vary significantly, it is difficult to directly compare the vulnerability of the implementations used in each. Research is necessary to identify and develop standard methods of evaluating the vulnerability of cryptographic implementations to PAAs. This thesis defines methodologies for performing PAAs on hardware implementations of AES. The process is divided into identification, extraction, and evaluation stages. The extraction stage is outlined for both simulated power consumption waveforms as well as for waveforms captured from physical implementations. An AES encryption hardware design is developed for the experiment. The hardware design is synthesized with the Synopsys 130-nm CMOS standard cell library. Simulated instantaneous power consumption waveforms are generated with Synopsys PrimeTime PX. Single and multiple-bit DPA attacks are performed on the waveforms. Improvements are applied in order to automate and improve the precision and performance of the system. The attacks on the simulated power waveforms are successful. The correct key byte is identified in 15 of the 16 single-bit attacks after 10,000 traces. The single-bit attack which does not uniquely identify the correct key byte becomes successful after 15,000 or more traces are applied. The key byte is found in 36 of the 38 multiple-bit attacks. The main contribution of this work is a methodology and simulation environment which can be used to design hardware which is resistant to PAA and determine and compare vulnerability.