Dielectric-Engineered High-Speed, Low-Power, Highly Reliable Charge Trap Flash-Based Synaptic Device for Neuromorphic Computing beyond Inference.

MLA

Kim, Joon Pyo, et al. “Dielectric-Engineered High-Speed, Low-Power, Highly Reliable Charge Trap Flash-Based Synaptic Device for Neuromorphic Computing beyond Inference.” Nano Letters, vol. 23, no. 2, Jan. 2023, pp. 451–61. EBSCOhost, https://doi.org/10.1021/acs.nanolett.2c03453.

APA

Kim, J. P., Kim, S. K., Park, S., Kuk, S.-H., Kim, T., Kim, B. H., Ahn, S.-H., Cho, Y.-H., Jeong, Y., Choi, S.-Y., & Kim, S. (2023). Dielectric-Engineered High-Speed, Low-Power, Highly Reliable Charge Trap Flash-Based Synaptic Device for Neuromorphic Computing beyond Inference. Nano Letters, 23(2), 451–461. https://doi.org/10.1021/acs.nanolett.2c03453

Chicago

Kim, Joon Pyo, Seong Kwang Kim, Seohak Park, Song-Hyeon Kuk, Taeyoon Kim, Bong Ho Kim, Seong-Hun Ahn, et al. 2023. “Dielectric-Engineered High-Speed, Low-Power, Highly Reliable Charge Trap Flash-Based Synaptic Device for Neuromorphic Computing beyond Inference.” Nano Letters 23 (2): 451–61. doi:10.1021/acs.nanolett.2c03453.