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Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.
Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.
- Source :
-
ACS applied materials & interfaces [ACS Appl Mater Interfaces] 2016 Jul 27; Vol. 8 (29), pp. 19110-8. Date of Electronic Publication: 2016 Jul 12. - Publication Year :
- 2016
-
Abstract
- Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native SiOx/GeOx surface layers, where the GeOx-rich layer is beneath a SiOx-rich surface. Silicon oxide regrows on the SiGe surface during Al2O3 atomic layer deposition, and both SiOx and GeOx regrow during forming gas anneal in the presence of a Pt gate metal. The resulting mixed SiOx-GeOx interface layer causes large interface trap densities (Dit) due to distorted Ge-O bonds across the interface. In contrast, we observe that oxygen-scavenging Al top gates decompose the underlying SiOx/GeOx, in a selective fashion, leaving an ultrathin SiOx interfacial layer that exhibits dramatically reduced Dit.
Details
- Language :
- English
- ISSN :
- 1944-8252
- Volume :
- 8
- Issue :
- 29
- Database :
- MEDLINE
- Journal :
- ACS applied materials & interfaces
- Publication Type :
- Academic Journal
- Accession number :
- 27345195
- Full Text :
- https://doi.org/10.1021/acsami.6b03331