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Diamond logic inverter with enhancement-mode metal-insulatorsemiconductor field effect transistor.

Authors :
Liu, J. W.
Liao, M. Y.
Imura, M.
Watanabe, E.
Oosato, H.
Koide, Y.
Source :
Applied Physics Letters. 8/25/2014, Vol. 105 Issue 8, p1-4. 4p. 1 Diagram, 3 Graphs.
Publication Year :
2014

Abstract

A diamond logic inverter is demonstrated using an enhancement-mode hydrogenated-diamond metal-insulator-semiconductor field effect transistor (MISFET) coupled with a load resistor. The gate insulator has a bilayer structure of a sputtering-deposited LaAlO3 layer and a thin atomiclayer-deposited Al2O3 buffer layer. The source-drain current maximum, extrinsic transconductance, and threshold voltage of the MISFET are measured to be --40.7 mA.mm-1, 13.2 ± 0.1 mS.mm-1, and --3.1 ± 0.1 V, respectively. The logic inverters show distinct inversion (NOT-gate) characteristics for input voltages ranging from 4.0 to --10.0 V. With increasing the load resistance, the gain of the logic inverter increases from 5.6 to as large as 19.4. The pulse response against the high and low input voltages shows the inversion response with the low and high output voltages. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00036951
Volume :
105
Issue :
8
Database :
Academic Search Index
Journal :
Applied Physics Letters
Publication Type :
Academic Journal
Accession number :
97881277
Full Text :
https://doi.org/10.1063/1.4894291