Back to Search
Start Over
Impact of Interfacial Layer and Transition Region on Gate Current Performance for High-K Gate Dielectric Stack: Its Tradeoff With Gate Capacitance.
- Source :
-
IEEE Transactions on Electron Devices . Feb2003, Vol. 50 Issue 2, p433. 7p. 2 Black and White Photographs, 2 Diagrams, 5 Graphs. - Publication Year :
- 2003
-
Abstract
- Stacked gate dielectrics are modeled with respect to the impact on the leakage current of interfacial layers and transition regions, considering the tradeoff with the gate capacitance. A Franz 2-band dispersion model is used. Low-EOT and low-gatecurrent regimes are explored theoretically using reasonable estimates guided by experimental data. Transition layer values of each parameter are qualitatively explored for oxynitride, Si[sub 3]N[sub 4]/SiO[sub 2], and high-K stacks. Higher dielectric constant and more insulating materials are obviously desired for each layer of dielectric; however, the transition region becomes more important as such dielectrics are considered. Higher dielectric constant of interfacial layer is desirable for the low-EOT-low-gate-current requirement. [ABSTRACT FROM AUTHOR]
- Subjects :
- *DIELECTRICS research
*GATE array circuits
*ELECTRIC capacity
*MODELS & modelmaking
Subjects
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 50
- Issue :
- 2
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 9685081
- Full Text :
- https://doi.org/10.1109/TED.2003.809433