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3D EDA brings together proven 2D solutions.

Authors :
KORCZYNSKI, E. D.
Source :
Solid State Technology. May2014, Vol. 57 Issue 3, p36-37. 2p.
Publication Year :
2014

Abstract

The article offers information on three dimension (3D) through stacking multiple layers of integrated circuits (IC) helps in the expression of complementary metal oxide semiconductors (CMOS) technology. It focuses on stacking heterogeneous chips using through-silicon vias (TSV) to form multiple active IC layers on silicon substrate.

Subjects

Subjects :
*COMPLEMENTARY metal oxide semiconductors
*INTEGRATED circuits
*SILICON
*SUBSTRATES (Materials science)
*ALGEBRAIC stacks

Details

Language :
English
ISSN :
0038111X
Volume :
57
Issue :
3
Database :
Academic Search Index
Journal :
Solid State Technology
Publication Type :
Academic Journal
Accession number :
96260037

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